Maintaining a high yield in semiconductor fabrication processes continues to be a critical factor in reducing the costs of device fabrication. The continuous trend to increase integration and reduce feature size increases the complexity of maintaining process conditions that result in devices which satisfy specifications with high yield.
Once the design of an integrated circuit (IC) is completed and a mask set and process recipe have successfully produced chips with high yield, the challenges are not finished. Process conditions and/or tool function can change or drift over time, resulting in changes, which may cause an unacceptable level of chip failures. For example, a change in a tool that increases a line width can change timing, resulting in failure to meet a specification requirement.
Once a change in chip yield is observed, finding a solution is a difficult task. There may be many different reasons for the decline in yield, and the change in yield may be the result of a combination of parameters, which can independently cause yield reductions and/or may interact with each other. When a substantial fraction of the chips fail to meet a particular type of specification (e.g., speed, transistor leakage current), the chips that fail that same type of specification are grouped into a “failure bin”.
In some cases it is possible to identify a “key device” or performance parameter, such as transistor saturation current that is relevant to a particular failure bin. In such cases, modifying the key device parameter through a process recipe change may improve yield (at least for that failure bin). It may be hard to identify a key device if there is no significant shift due to any single recipe change.
In some cases, the decline in device yield is due to random defects (such as a unacceptable particle infiltration into the processing tool, causing short circuits between adjacent lines). In these situations, there is no “key device”, and the nature of the solution to improve yield is very different.
Engineering analysis takes a long time to identify the solution(s) that will restore the production line to an acceptable yield level. This problem is especially difficult if there are multiple reasons for the decline in yield. Engineers may be required to manually check hundreds of electrical parameters. Until this analysis is completed, yield problems continue, and many unacceptable chips may by produced, which can cause serious impact to costs and/or delivery schedules.
Improved methods and tools for analyzing yield problems are desired.